The need for high speed input/output (I/O) continues to increase as clock speeds increase. I/O transfers between chips on printed circuit boards (PCBs) are becoming increasingly fast. As clock speeds increase, high speed I/O becomes more difficult to realize due to shrinking bit times and set up and hold times not scaling well.
Typical I/O uses at least two lines to transfer data from one chip to another. One line is for the data signal and the other line is for a data strobe or data clock signal. Both the data signal and the data strobe or data clock signal are transmitted simultaneously from one chip to another through the two lines. At the receiving chip, the data strobe or data clock signal is used to latch in the data bits from the data signal. Skew between the data signal and the data strobe or data clock signal increases the difficulty of transmitting data at high speeds. Skew and other factors across the I/O can dramatically reduce the valid data eye to 50% or less of the data bit time.
In a typical data bus, data is transferred continuously requiring constant power to drive both the data signal and the data clock or data strobe signal. In addition, the data line and the data strobe or data clock line must be routed precisely to avoid skew problems. Some designs need more data clock or data strobe lines as the data bus gets wider. In addition, adjacent data bits in the data bus may be switching in different directions during a half cycle of the data clock, which can cause crosstalk issues and simultaneous switching issues. The bits that are switching in typical I/O are held at ground or full power, which also increases crosstalk issues.
I/O can also suffer from a lone pulse problem. A lone pulse problem occurs when there are a series of logic low data bits or a series of logic high data bits and at one point in the series a single bit having the opposite logic level is transmitted. When this occurs, the opposite logic level data bit can be missed as the logic level of the data line may have been pulled too high or too low by the preceding multiple logic high bits or multiple logic low bits. A single bit of the opposite logic level may not overcome the threshold logic level required to characterize the bit. These problems become more common and troublesome as I/O speeds increase.